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./ LATCHRAMADDRESS BUSL2 CACHEµPINTERNALEVENCACHEDATA BUSCACHECONTROLLERON BOARDODD486 OR NEWERCACHEL1 CACHEChapter 6 System Boards429Both types of RAM are brought together to create an improvedDRAM, referred to as enhanced DRAM (EDRAM).By integratingan SRAM component into a DRAM device, a performance im-provement of 40% can be gained.An independent write pathallows the system to input new data without affecting the opera-tion of the rest of the chip.These devices are used primarily in L2cache memories.SRAM is available in a number of different types:.Asynchronous SRAM is standard SRAM and delivers datafrom the memory to the microprocessor and returns it tothe cache in one clock cycle.Synchronous SRAM uses special buffer storage to deliverdata to the CPU in one clock cycle after the first cycle.Thefirst address is stored and retrieves the data while the nextaddress is on its way to the cache.Pipeline SRAM uses three clock cycles to fetch the first dataand then accesses addresses within the selected page on eachclock cycle.Burst mode SRAM loads a number of consecutive data loca-tions from the cache, over several clock cycles, based on asingle address from the microprocessor.Memory Paging and InterleavingThere are also other commonly used methods of organizing RAMmemory so that it can be accessed more efficiently.Typically,memory accesses occur in two fashions: instruction fetches (whichare generally sequential), and operand accesses (which tend to berandom).Paging and interleaving memory schemes are designedto take advantage of the sequential nature of instruction fetchesfrom memory.The basic idea of paged-mode DRAM operations is illustrated inFigure 6.34.Special memory devices called page-mode (or static-column) RAM are required for memory paging structures.In theseA+ Certification Training Guide430memory devices, data is organized into groups of rows and col-umns called pages.After a ROW access is made in the device, it ispossible to access other column addresses within the same rowwithout precharging its Row Address Strobe (RAS) line.This fea-ture produces access times that are half that of normal DRAMmemories.Fast page mode RAM is a quicker version of page modeRAM having improved CAS access speed.Figure 6.34RASPage modeTcpDRAM operation.CASADDR ROW COLUMN COLUMN COLUMN COLUMN COLUMNDATA VALID VALID VALID VALID VALIDThe operating principle behind memory interleaving is described inFigure 6.35.Typical interleaving schemes divide the memory intotwo banks of RAM, with one bank storing even addresses and theother storing odd addresses.The RAS signals of the two banksoverlap so that the time required to precharge one bank s RAS lineis used for the active RAS time of the other bank.Therefore, thereshould never be a precharge time for either bank so long as theaccesses continue to be sequential.If a nonsequential access oc-curs, a miss is encountered and a wait state must be inserted inthe timing.If the memory is organized into two banks, the opera-tion is referred to as two-way interleaving.It is also common toorganize the memory into four, equal-sized banks.This organiza-tion effectively doubles the average 0-wait state hit space in thememory.TrpFigure 6.35RAS0Memory interleav-ing.CAS0DATA DATA1 DATA2 DATA1 DATA2 DATA1 DATA2RAS1CAS1Chapter 6 System Boards431Other RAM TypesAnother modified DRAM, referred to as synchronous DRAM(SDRAM), uses special internal registers and clocks to organizedata requests from memory.This allows the microprocessor toperform other tasks while the data is being organized.Extended Data Out (EDO) memory increases the speed at whichRAM operations are conducted by cutting out the 10-nanosecondwait time normally required between issuing memory addresses.This is accomplished by not disabling the data bus pins betweenbus cycles.EDO is an advanced type of fast page mode RAM alsoreferred to as hyper page mode RAM.The advantage of EDO RAM isencountered when multiple sequential memory accesses are per-formed [ Pobierz caÅ‚ość w formacie PDF ]